Magneto-resistance random access memory (MRAM) is attractive as a form of memory in many applications. It is capable of being integrated on-chip within the standard integrated circuit (IC) architecture. MRAM is non-volatile, not requiring power to maintain a memory state, i.e., the memory state is not lost in the event of a power loss. MRAM is based on writing and reading a tunneling resistance value of a magneto-resistive tunnel junction (MTJ). A MRAM bitcell includes an MTJ cell and a switch, which may be a transistor, for example. An MTJ cell is a junction having a fixed polarization magnetic layer and a free (i.e., re-writable) polarization magnetic layer separated by an electrically insulating tunneling layer.
In conventional MRAM, the free layer polarization is written by imposing an external magnetic field of sufficient strength. The tunneling resistance may commonly have two values depending on whether the free layer polarization is parallel or anti-parallel to the fixed layer. The tunneling resistance is lower in the parallel polarization state than in the anti-parallel polarization state.
Spin torque transfer (STT) MRAM is a form of MRAM where a reversible external magnetic field is not required to toggle the free layer polarization. This is accomplished by applying a sufficient density of spin polarized electron current through the junction. Parallel polarization occurs when the electrons in a write current flow from the fixed to the free layer. Anti-parallel polarization occurs when the write current flows in the opposite direction. Read current densities are generated by voltages that are too small to switch the free layer polarization, but otherwise operate in a similar manner, to measure the tunneling resistance and thereby determine the state of the MTJ cell.
Just as in standard IC testing, large arrays of memory may require testing of every memory cell. One part of testing is the characterization of read/write (R/W) speeds and critical currents, current densities and voltages. The amount of current density (as determined by the amount of applied voltage) required and the pulse width required to perform either read or write functions reliably may be measured.
STT MRAM has the capability to provide relatively high speed, low power, non-volatile memory. The (R/W) speed may be less than 1 nanosecond (ns). Pulse width characterization should therefore extend from less than 1 ns to effective DC. However, conventional test equipment may not be capable of providing sub-nanosecond pulse width signals. Standard testers, such as the Advantest T5585 memory tester (Advantest America Corporation, Santa Clara, Calif.) may have a minimum pulse width of 1 ns, for example, and may also have a maximum available pulse width (e.g., commonly a few ms). Furthermore, off-chip and on-chip capacitance, inductance and resistance existing between the tester port and the MTJ cell on-chip may prevent accurate measurements at the highest speeds, i.e., sub-nanosecond pulse widths, preventing an accurate determination of how fast the MTJ cell may be capable of operating in read and write modes.
In the interest of performance, including without limitation, power consumption, where battery life may be extended in portable applications, it is desirable to determine the least amount of power required to read and write to a memory bitcell based on the minimum pulse width and voltage required.